BSIM4 gate leakage model including source-drain partition

K. M. Cao*, W. C. Lee, W. Liu, X. Jin, Pin Su, S. K.H. Fung, J. X. An, B. Yu, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

155 Scopus citations

Abstract

Gate dielectric leakage current becomes a serious concern as sub-20Å gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.

Original languageEnglish
Pages (from-to)815-818
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 2000
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: 10 Dec 200013 Dec 2000

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