BSIM-CMG: Standard FinFET compact model for advanced circuit design

Juan P. Duarte, Sourabh Khandelwal, Aditya Medury, Chen-Ming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh S. Chauhan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

26 Scopus citations

Abstract

This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG model's capabilities for circuit design using FinFET transistors for advanced technology nodes.

Original languageEnglish
Title of host publicationESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
EditorsFranz Dielacher, Wolfgang Pribyl, Gernot Hueber
PublisherIEEE Computer Society
Pages196-201
Number of pages6
ISBN (Electronic)9781467374705
DOIs
StatePublished - 30 Oct 2015
Event41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
Duration: 14 Sep 201518 Sep 2015

Publication series

NameEuropean Solid-State Circuits Conference
Volume2015-October
ISSN (Print)1930-8833

Conference

Conference41st European Solid-State Circuits Conference, ESSCIRC 2015
CountryAustria
CityGraz
Period14/09/1518/09/15

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