A turnkey, production circuit simulation ready compact model for cylindrical/surround gate transistors has been developed. The core of the model contains an enhanced surface potential based description of the charge in the channel. Analytical expressions for channel current and terminal charges have been derived. A method to account for quantum confinement in the cylindrical structure in a compact model framework is described. For the first time we present calibration results of such a model to a cylindrical gate technology that also exhibits asymmetric I-V characteristics.
- Berkeley short-channel insulated-gate FET model (BSIM)
- Compact modeling
- Cylindrical gate
- Spice model
- Surround gate