BRAM efficient multi-ported memory on FPGA

Jiun Liang Lin, Bo-Cheng Lai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.

Original languageEnglish
Title of host publication2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479962754
DOIs
StatePublished - 28 May 2015
Event2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
Duration: 27 Apr 201529 Apr 2015

Publication series

Name2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
CountryTaiwan
CityHsinchu
Period27/04/1529/04/15

Keywords

  • BRAM efficient
  • FPGA
  • multi-ported memory

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