Boundary scan BIST methodology for reconfigurable systems

Chau-Chin Su; Shung Won Jeng; Yue Tsang Chen

doi:10.1109/TEST.1998.743260

Boundary scan BIST methodology for reconfigurable systems

Chau-Chin Su^*, Shung Won Jeng, Yue Tsang Chen

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

The interconnect BIST is achieved by the on-line polling for the composite vectors that contain the encoded information for the test generation and response evaluation on selective drivers and receivers to adapt to the changing configuration.

Original language	English
Title of host publication	IEEE International Test Conference (TC)
Editors	Anon
Pages	774-783
Number of pages	10
DOIs	https://doi.org/10.1109/TEST.1998.743260
State	Published - 1 Dec 1998
Event	Proceedings of the 1998 IEEE International Test Conference - Washington, DC, USA Duration: 18 Oct 1998 → 21 Oct 1998

Publication series

Name	IEEE International Test Conference (TC)
ISSN (Print)	1089-3539

Conference

Conference	Proceedings of the 1998 IEEE International Test Conference
City	Washington, DC, USA
Period	18/10/98 → 21/10/98

Access to Document

10.1109/TEST.1998.743260

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title = "Boundary scan BIST methodology for reconfigurable systems",

abstract = "The interconnect BIST is achieved by the on-line polling for the composite vectors that contain the encoded information for the test generation and response evaluation on selective drivers and receivers to adapt to the changing configuration.",

author = "Chau-Chin Su and Jeng, {Shung Won} and Chen, {Yue Tsang}",

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M3 - Conference contribution

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BT - IEEE International Test Conference (TC)

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