Block-level thermal model for floorplan stage in VLSI design flow

Shun Hua Lin*, Jin Tai Yan, Her-Ming Chiueh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Thermal issues have become a determinant factor to result in very large scale integrated (VLSI) circuits work or malfunction. For this reason, the paper proposed an efficient block-level thermal model for temperature calculation in the floorplan stage among the integrated circuit (IC) design flow. Furthermore, the model accurately profiles the temperature difference between all thermal blocks and overcomes the very long computational time issue existing in traditional tile-based thermal model. We not only prove the timing complexity by theory but also use five floorplan benchmarks to test our model. Observing the experimental results, the temperature calculation times for all benchmarks are really direct ratio of total amount of blocks. Hence our block-level thermal model really can reduce the temperature calculating time and provide useful temperature differences for rearranging the floorplan.

Original languageEnglish
Title of host publication14th International Workshop on Thermal Investigation of ICs and Systems, THERMINIC 2008
Pages58-63
Number of pages6
DOIs
StatePublished - 22 Dec 2008
Event14th International Workshop on THERMal INvestigation of ICs and Systems, THERMINIC 2008 - Rome, Italy
Duration: 24 Sep 200826 Sep 2008

Publication series

Name14th International Workshop on THERMal INvestigation of ICs and Systems, THERMINIC 2008

Conference

Conference14th International Workshop on THERMal INvestigation of ICs and Systems, THERMINIC 2008
CountryItaly
CityRome
Period24/09/0826/09/08

Fingerprint Dive into the research topics of 'Block-level thermal model for floorplan stage in VLSI design flow'. Together they form a unique fingerprint.

Cite this