Bit-error-rate analysis for clock and data recovery based on blind oversampling technique

Shyh-Jye Jou*, Chih Hsien Lin, Yen I. Wang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper, we propose the bit-error-rate (BER) estimation and architecture designs for the digital data recovery using a blind oversampling method that meets BER and jitter tolerance specifications. The blind oversampling method is suitable for the burst mode receiver due to low locking time. The proposed architecture is very regular and hence very suitable for standard cell implementation flow. Thus it is very suitable as a soft silicon intellectual property (SIP). Therefore, several key performance and design parameters such as jitter of data and clock, sliding windows and oversampling ratio with respect to BER or jitter tolerance mask must be formulated that different specifications can be designed with different design parameters. The proposed statistical analysis methodology enables quick verification of the BER for various kinds of circuit architecture.

Original languageEnglish
Pages (from-to)219-228
Number of pages10
JournalInternational Journal of Electrical Engineering
Volume13
Issue number3
StatePublished - 1 Aug 2006

Keywords

  • Bit-error-rate
  • Clock and data recovery
  • Oversampling

Fingerprint Dive into the research topics of 'Bit-error-rate analysis for clock and data recovery based on blind oversampling technique'. Together they form a unique fingerprint.

Cite this