In this paper, we propose the bit-error-rate (BER) estimation and architecture designs for the digital data recovery using a blind oversampling method that meets BER and jitter tolerance specifications. The blind oversampling method is suitable for the burst mode receiver due to low locking time. The proposed architecture is very regular and hence very suitable for standard cell implementation flow. Thus it is very suitable as a soft silicon intellectual property (SIP). Therefore, several key performance and design parameters such as jitter of data and clock, sliding windows and oversampling ratio with respect to BER or jitter tolerance mask must be formulated that different specifications can be designed with different design parameters. The proposed statistical analysis methodology enables quick verification of the BER for various kinds of circuit architecture.
|Number of pages||10|
|Journal||International Journal of Electrical Engineering|
|State||Published - 1 Aug 2006|
- Clock and data recovery