Bipolar transistor design for low process-temperature 0.5 μm Bi-CMOS

M. Norishima*, Y. Niitsu, G. Sasaki, H. Iwai, K. Maeguchi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

A low-temperature (800-850°C) processed bipolar transistor design suitable for high-performance 0.5-μm BiCMOS process is discussed. It was found that insufficient activation of arsenic in the emitter, fast base boron diffusion in the low-concentration region caused by implantation damages for the direct-ion-implanted emitter case, and insufficient arsenic diffusion from the poly-Si for the poly-Si emitter case should be considered as serious problems when the low-temperature furnace anneal is used. High-temperature RTA (rapid thermal annealing) is shown to solve those problems. Based on the impurity diffusion behaviors and related electric bipolar characteristics, the optimum conditions and structures for bipolar transistor design for the high-performance 0.5-μm BiCMOS process are discussed.

Original languageEnglish
Pages (from-to)237-240
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 1989
Event1989 International Electron Devices Meeting - Technical Digest - Washington, DC, USA
Duration: 3 Dec 19896 Dec 1989

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