Hot carrier induced bipolar transistor degradation under dynamic stress is studied. The model, ΔIB ∝ (IR1.8 t)0.5, established from d.c. emitter-base reverse bias stress measurements is found to be still valid under pulse stress down to 20 ns pulse width, where ΔIB is drift of base current, IR is reverse emitter-base current under stress and t is stress time. Although partial degradation recovery is observed under d.c. emitter-base forward bias, ΔIB from alternating reverse-forward stress representative BiCMOS circuit operation agrees with the ΔIB model with no significant recovery effect. This is explained by a higher degradation rate after recovery of previous damage. An experimental basis of BiCMOS circuit reliability testing simulation is thus provided.