Bipolar Dual-LFSR Reseeding for Low-Power Testing

Jen Cheng Ying, Wang Dauh Tseng, W. J. Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Large test data volume and excessive test power are two strict challenges for VLSI circuit testing. Built-in self-Test (BIST) is recognized as a good solution to the problem of large test data volume. LFSR-decompressor-based compression methods have been widely adopted in BIST to reduce test data volume. The effectiveness of this approach is on the ability to control the generated pseudorandom pattern. This paper adopts dual-LFSR to effectively reduce the amount of test data while keeping the scan-in power as low. Experimental results show that it has a significant reduction of data volume and test power using the proposed new Bipolar Dual-LFSR reseeding approach as compared to the existing related dual-LFSR schemes.

Original languageEnglish
Title of host publicationDSC 2018 - 2018 IEEE Conference on Dependable and Secure Computing
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538657904
DOIs
StatePublished - 23 Jan 2019
Event2018 IEEE Conference on Dependable and Secure Computing, DSC 2018 - Kaohsiung, Taiwan
Duration: 10 Dec 201813 Dec 2018

Publication series

NameDSC 2018 - 2018 IEEE Conference on Dependable and Secure Computing

Conference

Conference2018 IEEE Conference on Dependable and Secure Computing, DSC 2018
CountryTaiwan
CityKaohsiung
Period10/12/1813/12/18

Keywords

  • BIST
  • dual LFSR
  • low power testing
  • test data compression

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  • Cite this

    Ying, J. C., Tseng, W. D., & Tsai, W. J. (2019). Bipolar Dual-LFSR Reseeding for Low-Power Testing. In DSC 2018 - 2018 IEEE Conference on Dependable and Secure Computing [8625105] (DSC 2018 - 2018 IEEE Conference on Dependable and Secure Computing). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DESEC.2018.8625105