Bipolar circuit reliability simulation

David Burnett*, Tadahiko Horiuchi, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference article

8 Scopus citations

Abstract

A model for bipolar hot-carrier degradation has been implemented into the BERT circuit reliability simulator, thus allowing both bipolar and BiCMOS circuit degradation to be simulated. The bipolar module consists of a preprocessor and post-processor for SPICE that require no modification to the SPICE code. Experimental results indicate that the degradation due to alternating reverse-forward stressing representative of BiCMOS gate operation agrees with the ΔIB model from DC measurements. The base current degradation for a single device due to electrostatic discharge stress and the offset voltage degradation for an emitter-coupled pair due to DC stress are accurately predicted by the simulator.

Original languageEnglish
Pages (from-to)181-184
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 1990
Event1990 International Electron Devices Meeting - San Francisco, CA, USA
Duration: 9 Dec 199012 Dec 1990

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