A model for bipolar hot-carrier degradation has been implemented into the BERT circuit reliability simulator, thus allowing both bipolar and BiCMOS circuit degradation to be simulated. The bipolar module consists of a preprocessor and post-processor for SPICE that require no modification to the SPICE code. Experimental results indicate that the degradation due to alternating reverse-forward stressing representative of BiCMOS gate operation agrees with the ΔIB model from DC measurements. The base current degradation for a single device due to electrostatic discharge stress and the offset voltage degradation for an emitter-coupled pair due to DC stress are accurately predicted by the simulator.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 1990|
|Event||1990 International Electron Devices Meeting - San Francisco, CA, USA|
Duration: 9 Dec 1990 → 12 Dec 1990