Bias polarity dependent effects of P+ floating gate EEPROMs

Charles Kuo*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


EEPROM devices with either N-type or P-type floating gate were fabricated and characterized. Program/erase speeds and stress-induced leakage current-related retention characteristics for both types of devices are explained. Discrepancies between previously published reports on P-type floating gate devices and PMOS gate current measurements are resolved. The feasibility of integrating P-type floating gate EEPROMs in high density memory arrays is examined.

Original languageEnglish
Pages (from-to)282-285
Number of pages4
JournalIEEE Transactions on Electron Devices
Issue number2
StatePublished - 1 Feb 2004


  • Flash memories
  • Nonvolatile semiconductor memories
  • Scaling

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