Bi-Mode Breakdown Test Methodology of Ultrathin Oxide

Hung Der Su*, Bi Shiou Chiou, Chin Yuan Ko, Shien Yang Wu, Ming Hsung Chang, Kuo Hua Lee, Yung Shun Chen, Chih Ping Chao, Yee Chaung See, Jack Yuan Chen Sun

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


The breakdown detections of ultrathin oxide (1.4-2 nm) using a fast voltage ramp have been studied. It was found that the breakdown voltage test of deep sub-micron technology requires the reduction of the gate area of test patterns and therefore the increase of the number of structures due to a large inversion gate current at a low electrical field (> 0.1 A/cm2 at 1 V) caused by the scaling down of oxide thickness. The gate current in accumulation mode is smaller than that in inversion mode by more than two orders of magnitude at a low applied voltage (1V). The bi-mode model proposed in this paper applies a voltage stress in the inversion mode and detects failure in the accumulation mode to enhance the robustness of the breakdown test and reduce the possibility of pseudo breakdown failure. With the proposed method, a shorter test time with an increased test pattern area to improve the efficiency of the breakdown test of ultrathin oxide is achieved.

Original languageEnglish
Pages (from-to)7232-7237
Number of pages6
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Issue number12
StatePublished - Dec 2003


  • Bi-mode
  • Oxide breakdown
  • Ramped voltage
  • Reliability
  • Ultrathin oxide

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