Behavior-level yield enhancement approach for large-scaled analog circuits

Chin Cheng Kuo*, Yen Lung Chen, I. Ching Tsai, Li Yu Chan, Chien-Nan Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation efforts, this work tries to finish all iteration steps of the yield enhancement flow at behavior level. First, a novel force-directed nominal point moving (NPM) algorithm is proposed to find a better nominal point without building the feasible regions. Then, an equation-based behavior-level sizing approach is proposed to map the NPM results at performance level to behavior-level parameters. A fast behavior-level Monte Carlo simulation is also proposed to shorten the iterative yield enhancement flow. Finally, using the obtained behavioral parameters as the sizing targets of each sub-block, the device sizing time is significantly reduced instead of sizing from the system-level specifications directly. As demonstrated on a complex CPPLL design, this behavior-level approach could be another efficient methodology to help designers improve their analog circuits toward better yield.

Original languageEnglish
Title of host publicationProceedings of the 47th Design Automation Conference, DAC '10
Number of pages6
StatePublished - 7 Sep 2010
Event47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
Duration: 13 Jun 201018 Jun 2010

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Conference47th Design Automation Conference, DAC '10
CountryUnited States
CityAnaheim, CA


  • Analog circuits
  • Process variation
  • Yield enhancement

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