Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off

Ya-Chi Cheng; Hung Bin Chen; Chun-Yen Chang; Yi-Kang Wu; Yi-Jia Shih; Chi-Shen Shao; Yung-Chun Wu

doi:10.1063/1.4935247

Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off

Ya-Chi Cheng, Hung Bin Chen, Chun-Yen Chang, Yi-Kang Wu, Yi-Jia Shih, Chi-Shen Shao, Yung-Chun Wu

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.

Original language	English
Journal	Applied Physics Letters
Volume	107
Issue number	18
DOIs	https://doi.org/10.1063/1.4935247
State	Published - 2 Nov 2015

Keywords

SUBSTRATE BIAS

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title = "Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off",

abstract = "A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.",

keywords = "SUBSTRATE BIAS",

author = "Ya-Chi Cheng and Chen, {Hung Bin} and Chun-Yen Chang and Yi-Kang Wu and Yi-Jia Shih and Chi-Shen Shao and Yung-Chun Wu",

year = "2015",

month = nov,

day = "2",

doi = "10.1063/1.4935247",

language = "English",

volume = "107",

journal = "Applied Physics Letters",

issn = "0003-6951",

publisher = "American Institute of Physics",

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TY - JOUR

T1 - Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off

AU - Cheng, Ya-Chi

AU - Chen, Hung Bin

AU - Chang, Chun-Yen

AU - Wu, Yi-Kang

AU - Shih, Yi-Jia

AU - Shao, Chi-Shen

AU - Wu, Yung-Chun

PY - 2015/11/2

Y1 - 2015/11/2

N2 - A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.

AB - A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.

KW - SUBSTRATE BIAS

U2 - 10.1063/1.4935247

DO - 10.1063/1.4935247

M3 - Article

VL - 107

JO - Applied Physics Letters

JF - Applied Physics Letters

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