A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.
- SUBSTRATE BIAS
Cheng, Y-C., Chen, H. B., Chang, C-Y., Wu, Y-K., Shih, Y-J., Shao, C-S., & Wu, Y-C. (2015). Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off. Applied Physics Letters, 107(18). https://doi.org/10.1063/1.4935247