Avalanche ruggedness capability and improvement of 5-v n-channel large-array mosfet in bcd process

Karuna Nidhi, Ming-Dou Ker*, Jian Hsing Lee, Shao Chang Huang

*Corresponding author for this work

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (IAV) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12μm.

Original languageEnglish
Article number8723307
Pages (from-to)3040-3048
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume66
Issue number7
DOIs
StatePublished - 1 Jul 2019

Keywords

  • Avalanche ruggedness
  • Avalanche safe-operating-area (A-SOA)
  • Current in avalanche (IAV)
  • Large-array device (LAD)
  • Time in avalanche (tAV)
  • Total gate charge (Qg)
  • Unclamped inductive switching (UIS)

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