Automatic verification stimulus generation for interface protocols modeled with non-deterministic extended FSM

Che Hua Shih*, Juinn-Dar Huang, Jing Yang Jou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Verifying if an integrated component is compliant with certain interface protocol is a vital issue in component-based system-on-a-chip (SoC) designs. For simulation-based verification, generating massive constrained simulation stimuli is becoming crucial to achieve a high verification quality. To further improve the quality, stimulus biasing techniques are often used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the non-deterministic extended finite-state machine (NEFSM), and then propose an automatic stimulus generation approach based on it. This approach is capable of providing numerous biasing strategies. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.

Original languageEnglish
Article number4799218
Pages (from-to)723-727
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume17
Issue number5
DOIs
StatePublished - 1 May 2009

Keywords

  • Design automation
  • Generators

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