Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's

Ming-Dou Ker*, Hsin Chin Jiang, Jeng Jie Peng, Tzay Luen Shieh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.

Original languageEnglish
Title of host publicationICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages113-116
Number of pages4
DOIs
StatePublished - 1 Dec 2001
Event8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta
Duration: 2 Sep 20015 Sep 2001

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume1

Conference

Conference8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
CountryMalta
Period2/09/015/09/01

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    Ker, M-D., Jiang, H. C., Peng, J. J., & Shieh, T. L. (2001). Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. In ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems (pp. 113-116). [957690] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1). https://doi.org/10.1109/ICECS.2001.957690