Automatic loading detection (ALD) technique for 92% high efficiency interleaving power factor correction (PFC) over a wide output power of 180W

Jen Chive Tsai, Chun Yen Chen, Yi Ting Chen, Chia Lung Ni, Yi Ping Su, Ke-Horng Chen, Yu Wen Chen, Chao Chiun Liang, Chang An Ho, Tun Hao Yu

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

The proposed automatic loading detection (ALD) technique keeps high efficiency in interleaving power factor correction (PFC) over a wide load range. With the advantages of small input/output filter and output ripple in the interleaving mechanism, the improved efficiency by the ALD technique at light loads due to reduced switching loss can be widely used in the adapter of portable electronics. The ALD technique can calculate the power by the detection of peak input voltage to reduce the switching loss since the slave channel can be completely turned off for power saving at light loads. Therefore, the boundary control mode (BCM) control can simultaneously provide high power and keep high conversion efficiency both at light and heavy loads. The highly integrated PFC controller fabricated in TSMC 800V UHV process shows high efficiency of 92% over a wide output power of 180 W.

Original languageEnglish
Pages229-232
Number of pages4
DOIs
StatePublished - 1 Dec 2012
Event2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
Duration: 12 Nov 201214 Nov 2012

Conference

Conference2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
CountryJapan
CityKobe
Period12/11/1214/11/12

Keywords

  • automatic loading detection (ALD) technique
  • interleaving power factor correction (PFC)
  • switching power loss

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