While the coverage-driven design validation is getting popular, it would be more convenient for users to have an automatic generator that can generate the input patterns to satisfy the coverage requirements. The symbolic techniques can be used to generate the desired input patterns easily for a specific state transition in a FSM. However, it is not practical for real designs because the memory requirement is often unmanageable. In this paper, we propose an automatic pattern generation engine that can overcome the memory issues for large circuits. It can generate all possible input combinations or notify that such cases will never happen for any specific state transitions. Because we can reasonably partition the HDL designs into the interacting FSM model, the peak memory requirement can be significantly reduced by using the "divide and conquer" strategy for those small FSMs. The experimental results show that we can indeed generate the required input patterns with reasonable memory requirement for the designs with thousands of registers.