Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC

Wei Hao Hsiao*, Yi Ting He, Po-Hung Lin, Rong Guey Chang, Shuenn Yuh Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous works only focused on common-centroid placement optimization with the consideration of random and systematic mismatch. This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on circuit accuracy/performance. Experimental results show that, compared with the manual layout, the layout generated by the presented approach can achieve even smaller layout area and better circuit accuracy/performance within much shorter time.

Original languageEnglish
Title of host publication2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
Pages173-176
Number of pages4
DOIs
StatePublished - 11 Dec 2012
Event2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 - Seville, Spain
Duration: 19 Sep 201221 Sep 2012

Publication series

Name2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012

Conference

Conference2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012
CountrySpain
CitySeville
Period19/09/1221/09/12

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    Hsiao, W. H., He, Y. T., Lin, P-H., Chang, R. G., & Lee, S. Y. (2012). Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC. In 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 (pp. 173-176). [6339445] (2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012). https://doi.org/10.1109/SMACD.2012.6339445