Automatic circuit adjustment technique for process sensitivity reduction and yield improvement

Hsiu Wen Li*, Ren Hong Fu, Hsin Yu Luo, Chien-Nan Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In deep submicron process, parametric yield loss due to process variations has become a critical issue, especially for sensitive analog circuits. Design centering is one of the popular techniques to find the nominal design that leads to the maximum yield. However, in critical cases, it is possible that some parts of the performance distribution are still outside the feasible region and has no way to further improve the yield. Therefore, a process sensitivity reduction flow for analog circuits is proposed in this paper. Without moving the given nominal point, a new set of device sizes that lead to smaller performance distribution range can be obtained in the proposed sizing flow, which helps to further improve the yield of that design.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages2582-2585
Number of pages4
DOIs
StatePublished - 31 Aug 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: 30 May 20102 Jun 2010

Publication series

NameISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Conference

Conference2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period30/05/102/06/10

Keywords

  • Analog
  • OTA
  • SA
  • Sensitivity
  • Yield

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