Asymmetrical write-assist for single-ended SRAM operation

Jihi Yu Lin*, Ming Hsien Tu, Ming Chien Tsai, Shyh-Jye Jou, Ching Te Chuang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this paper, asymmetrical Write-assist cell virtual ground biasing and positive feedback sensing keeper schemes are proposed to improve the Read Static Noise Margin (RSNM), Write Margin (WM), and operation speed of a singleended Read/Write 8T SRAM cell. A 4Kbit SRAM implemented in 90nm CMOS technology achieves 1uW/bit average power consumption at 6MHz, Vmin of 410mV at 6MHz, and 234MHz maximum operation frequency at 600mV.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2009
Pages101-104
Number of pages4
DOIs
StatePublished - 1 Dec 2009
EventIEEE International SOC Conference, SOCC 2009 - Belfast, Ireland
Duration: 9 Sep 200911 Sep 2009

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2009

Conference

ConferenceIEEE International SOC Conference, SOCC 2009
CountryIreland
CityBelfast
Period9/09/0911/09/09

Fingerprint Dive into the research topics of 'Asymmetrical write-assist for single-ended SRAM operation'. Together they form a unique fingerprint.

  • Cite this

    Lin, J. Y., Tu, M. H., Tsai, M. C., Jou, S-J., & Chuang, C. T. (2009). Asymmetrical write-assist for single-ended SRAM operation. In Proceedings - IEEE International SOC Conference, SOCC 2009 (pp. 101-104). [5398086] (Proceedings - IEEE International SOC Conference, SOCC 2009). https://doi.org/10.1109/SOCCON.2009.5398086