Assessment of technological device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs

M. Koyama, M. Cassé, S. Barraud, G. Ghibaudo, H. Iwai, G. Reimbold

Research output: Contribution to conferencePaper

4 Scopus citations

Abstract

We report an experimental investigation of oxide/channel interface quality in SOI omega-gate nanowire NMOS FETs with cross-section as small as 10nm×10nm by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, H2 anneal, or channel orientation. A method for rigorous contribution assessment of the two interfaces (top surface vs. side-walls) is also demonstrated. Excellent quality of the interfaces is extracted for all our technological and structural parameters.

Original languageEnglish
Pages57-60
Number of pages4
DOIs
StatePublished - 2014
Event2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014 - Stockholm, Sweden
Duration: 7 Apr 20149 Apr 2014

Conference

Conference2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014
CountrySweden
CityStockholm
Period7/04/149/04/14

Keywords

  • low-frequency noise
  • oxide trap density
  • SOI
  • strained-SOI
  • Ω-gate nanowire transistors

Fingerprint Dive into the research topics of 'Assessment of technological device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs'. Together they form a unique fingerprint.

  • Cite this

    Koyama, M., Cassé, M., Barraud, S., Ghibaudo, G., Iwai, H., & Reimbold, G. (2014). Assessment of technological device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs. 57-60. Paper presented at 2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014, Stockholm, Sweden. https://doi.org/10.1109/ULIS.2014.6813905