Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs

M. Koyama*, M. Cassé, S. Barraud, G. Ghibaudo, H. Iwai, O. Faynot, G. Reimbold

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm × 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors.

Original languageEnglish
Pages (from-to)36-41
Number of pages6
JournalSolid-State Electronics
Volume108
DOIs
StatePublished - Jun 2015

Keywords

  • Low-frequency noise
  • Omega-gate
  • Oxide trap density
  • Si nanowire MOSFETs
  • Strained-SOI
  • Surface orientation

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