Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications

Teng Chieh Huang, Po-Tsang Huang, Shang Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo Hua Chen, Chi Tsung Chiu, Ho Ming Tong, Ching Te Chuang, Wei Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

In this paper, an area-power-efficient 11-bit hybrid analog-to-digital converter (ADC) with delay-line enhanced tuning for neural sensing applications is presented. To reduce the total amount of capacitance, this hybrid ADC is composed of a coarse tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detect the three most significant bits by a modified vernier structure. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. To further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in TSMC 0.18μm CMOS technology, an ENOB of 10.4-bit at 8KS/s can be achieved with only 0.6μW power consumption and 0.032-mm2 area. The FoM of this ADC is 49.4fJ/conversion-step.

Original languageEnglish
Title of host publication2013 IEEE Biomedical Circuits and Systems Conference, BioCAS 2013
Pages238-241
Number of pages4
DOIs
StatePublished - 1 Dec 2013
Event2013 IEEE Biomedical Circuits and Systems Conference, BioCAS 2013 - Rotterdam, Netherlands
Duration: 31 Oct 20132 Nov 2013

Publication series

Name2013 IEEE Biomedical Circuits and Systems Conference, BioCAS 2013

Conference

Conference2013 IEEE Biomedical Circuits and Systems Conference, BioCAS 2013
CountryNetherlands
CityRotterdam
Period31/10/132/11/13

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