Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints

Yi Hang Chen*, Jian Yu Chen, Juinn-Dar Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

As fabrication processes exploit even deeper submicron technology, power dissipation has become a crucial issue for most electronic circuit and system designs nowadays. In particular, leakage power is becoming a dominant source of power consumption. Recently, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore's Law due to its ultra-low power consumption. Several automated synthesis approaches have been developed for the reconfigurable SET array in the past few years. Nevertheless, all of those existing methods consider fabrication constraints, which are mandatory, merely in late synthesis stages. In this paper, we propose a synthesis algorithm, featuring both variable reordering and product term reordering, for area minimization. In addition, our algorithm takes those mandatory fabrication constraints into account in early stages for better outcomes. Experimental results show that our new method can achieve an area reduction of up to 24% as compared to current state-of-the-art techniques.

Original languageEnglish
Title of host publication2014 Design, Automation and Test in Europe Conference and Exhibition (DATE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9783981537024
DOIs
StatePublished - 24 Mar 2014
Event17th Design, Automation and Test in Europe, DATE 2014 - Dresden, Germany
Duration: 24 Mar 201428 Mar 2014

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

Conference17th Design, Automation and Test in Europe, DATE 2014
CountryGermany
CityDresden
Period24/03/1428/03/14

Keywords

  • area minimization
  • automatic synthesis
  • binary decision diagram
  • reconfigurable
  • single-electron transistor

Fingerprint Dive into the research topics of 'Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints'. Together they form a unique fingerprint.

Cite this