Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection

Ming-Dou Ker*

*Corresponding author for this work

Research output: Contribution to conferencePaper

12 Scopus citations

Abstract

A novel substrate-triggering field-oxide device (STFOD) is proposed to form an area-efficient ESD clamp circuit for whole-chip ESD protection in submicron CMOS technology. Experimental results in a 0.6-μm CMOS process have verified that this STFOD can provide four-times higher ESD robustness in per unit layout area as comparing to the previous works with the NMOS device. This design has been practically implemented in an 8-bits DAC chip to provide a real whole-chip ESD protection of above 4 KV.

Original languageEnglish
Pages69-73
Number of pages5
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
Duration: 3 Jun 19975 Jun 1997

Conference

ConferenceProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
CityTaipei, China
Period3/06/975/06/97

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    Ker, M-D. (1997). Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection. 69-73. Paper presented at Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, Taipei, China, . https://doi.org/10.1109/VTSA.1997.614730