Area-efficient register organization for fully-synthesizable VLIW DSP cores

Tay Jyi Lin*, Chih-Wei Liu, Pi Chen Hsiao, Chein Wei Jen

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

Clustering and banking are two effective microarchitectural techniques to reduce the complexity of register files in wide-issue microprocessors. In this paper, we develop simple analytical formulae based on cell-based implementations with flip-flops and multiplexers, to describe and analyze the variants of them. We propose a simple inter-cluster communication mechanism with load/store instruction pairs and a novel distributed & ping-pong register organization for very-long-instruction-word (VLIW) DSP cores. In our simulations, the DSP with the proposed register file has comparable performance with state-of-the-art DSPs for popular DSP kernels. However, 76.8% area and 46.9% access time of its equivalent centralized register files are saved in the UMC 0.13μm 1P8M CMOS technology.

Original languageEnglish
Pages (from-to)117-127
Number of pages11
JournalInternational Journal of Electrical Engineering
Volume13
Issue number2
StatePublished - 1 May 2006

Keywords

  • And digital signal processor (DSP)
  • Banking
  • Clustering
  • Register file
  • Very long instruction word (VLIW)

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