Area-Efficient On-Chip Transient Detection Circuit for System-Level ESD Protection Against Transient-Induced Malfunction

Wen Chieh Chen, Ming-Dou Ker*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

A new on-chip transient detection circuit with superior area efficiency is proposed against the system malfunction resulting from system-level electrostatic discharge (ESD) events. With dual-latched structure, a better area efficiency can be achieved by the reduced time constant inquiry. The proposed transient detection circuit with a silicon area of 40 {\mu }\text{m}\,\,{\times }\,\,60\,\,{\mu }\text{m} has been fabricated in a 0.18-{\mu }\text{m} CMOS process with 1.8-V devices. The detection sensitivity has been successfully verified under ±200 V system-level ESD tests. To achieve the 'Class B' specification of IEC 61000-4-2 standard, the proposed transient detection circuit serves as a safety guard for the system. Through the hardware/firmware co-design, the auto-recovery procedure can be activated by the proposed transient detection circuit sending out a warning signal. With the proposed transient detection circuit co-works with the system program, the immunity level of microelectronic products against the electromagnetic compatibility (EMC) of ESD events can be effectively improved.

Original languageEnglish
Article number8686205
Pages (from-to)363-369
Number of pages7
JournalIEEE Transactions on Device and Materials Reliability
Volume19
Issue number2
DOIs
StatePublished - 1 Jun 2019

Keywords

  • Electrostatic discharge (ESD)
  • electromagnetic compatibility (EMC)
  • system-level ESD
  • transient detection circuit

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