Area-efficient maximum/minimum detection circuit for digital and video signal processing

Chen-Yi Lee*, Shih Chou Juan, Wen Wei Yang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a novel circuit for parallel bit-level maximum/minimum selection. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from MSB to LSB and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns as those required in digital and video signal processing.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages223-226
Number of pages4
ISBN (Print)0780312813
DOIs
StatePublished - 1 Jan 1993
Event1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
Duration: 3 May 19936 May 1993

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume1
ISSN (Print)0271-4310

Conference

Conference1993 IEEE International Symposium on Circuits and Systems
CityChicago, IL, USA
Period3/05/936/05/93

Fingerprint Dive into the research topics of 'Area-efficient maximum/minimum detection circuit for digital and video signal processing'. Together they form a unique fingerprint.

  • Cite this

    Lee, C-Y., Juan, S. C., & Yang, W. W. (1993). Area-efficient maximum/minimum detection circuit for digital and video signal processing. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 223-226). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 1). Publ by IEEE. https://doi.org/10.1109/ISCAS.1993.393698