Area-efficient instruction set extension exploration with hardware design space exploration

Instruction set extension (ISE) is an effective approach to improve the processor performance without tremendous modification in its core architecture. To execute ISE(s), a processor core must be augmented with a new functional unit, called application specific functional unit (ASFU), which consists of multiple hardware implementation options of ISEs (ISE-HW). Obviously, since ISE-HW increases the production cost of a processor core, minimizing the area size of ISE-HW becomes important for ISE exploration. On the other hand, because of different requirements in space and speed, ISE-HW usually has multiple hardware implementation options. Under pipeline-stage timing constraint, some of these options may have the same performance improvement but entail different hardware costs. According to this phenomenon, the area size of ISE-HW can be reduced by performing hardware design space exploration of ISE-HW. Therefore, in this paper, we propose an ISE exploration algorithm that explores not only ISE but also the hardware design space of ISE-HW. Compared with the previous research, our approach resulted in significant improvement in area efficiency and the execution performance.