Area-efficient ESD clamp circuit with a capacitance-boosting technique to minimize standby leakage current

Federico A. Altolaguirre, Ming-Dou Ker

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

This paper presents a new RC-based power-rail electrostatic discharge (ESD) clamp circuit, which achieves ultra-low leakage current while maintaining low silicon utilization. A capacitance- boosting technique is used in conjunction with mathematical analysis of area utilization to determine the best set of parameters to achieve the smallest implementation area in silicon. The proposed power-rail ESD clamp circuit has been verified in a 65-nm general-purpose CMOS process, which achieves an ultra-low standby leakage current of 80 nA at 25 7deg;C under 1-V bias, as well as ESD robustness of a 4-kV human body model and a 250-Vmachine model with a silicon area of only 45 μm × 17 μm.

Original languageEnglish
Article number7050329
Pages (from-to)156-162
Number of pages7
JournalIEEE Transactions on Device and Materials Reliability
Volume15
Issue number2
DOIs
StatePublished - 1 Jan 2015

Keywords

  • Electrostatic discharge (ESD)
  • ESD protection
  • Leakage
  • Power rail

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