Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

Ming-Dou Ker*, Kuo Feng Wang, Mei Chu Joe, Yuan Hua Chu, Tain Shun Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

11 Scopus citations

Abstract

There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC's. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000V (700V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-μm CMOS technology with LDD and polycide processes.

Original languageEnglish
Article number5218681
Pages (from-to)123-125
Number of pages3
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
StatePublished - 1 Dec 1995
EventProceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
Duration: 18 Sep 199522 Sep 1995

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