Architecture for area-efficient 2-D transform in H.264/AVC

Yu Ting Kuo*, Tay Jyi Lin, Chih-Wei Liu, Chein Wei Jen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

As the VLSI technology advances continuously, ASIC can easily achieve the required performance and most of them are actually over-designed. Thus, architecture shrinking is inevitable in optimal designs especially when supply voltages are getting lower. However, conventional designs starting from minimization of algorithmic operations (e.g. multiply) may not always lead to optimal architectures, for the wires and the interconnection complexity significantly grow and have become predominant. This paper explores algorithms and architectures for the 2-D transform in H.264/AVC, of which the operations are very simple (i.e. only shift and add). We have shown that fewer operations do not always result in more compact designs. In our experiments with the UMC 0.18μm CMOS technology, the most straightforward matrix multiplication without separable 2-D operation or any fast algorithm has the best area efficiency for D1-size (720×480) video at 30fps. It saves 48%, 34%, and 16% silicon area of the previous works respectively.

Original languageEnglish
Title of host publicationIEEE International Conference on Multimedia and Expo, ICME 2005
Pages1126-1129
Number of pages4
DOIs
StatePublished - 1 Dec 2005
EventIEEE International Conference on Multimedia and Expo, ICME 2005 - Amsterdam, Netherlands
Duration: 6 Jul 20058 Jul 2005

Publication series

NameIEEE International Conference on Multimedia and Expo, ICME 2005
Volume2005

Conference

ConferenceIEEE International Conference on Multimedia and Expo, ICME 2005
CountryNetherlands
CityAmsterdam
Period6/07/058/07/05

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