Architecture exploration and delay minimization synthesis for set-based programmable gate arrays

Chia Cheng Wu, Kung Han Ho, Juinn-Dar Huang, Chun Yao Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Power consumption has become a primary obstacle for circuit designs at present. Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its low power consumption. Since, only a few electrons are involved in the switching process, the drivability of SETs is ultra-low such that the height of an SET array is limited to a small number. This paper presents a delay minimization synthesis flow that decomposes a circuit into a network of SET Array Blocks (SABs) with a fixed height and width. The experiments were conducted for different sizes of SABs over a set of benchmarks. The experimental results showed that we can have the smallest average Area Delay Product (ADP) when the height is 5 and the width is 10 of an SAB, which indicates that such size of SABs is proper to synthesize SET networks.

Original languageEnglish
Title of host publicationProceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
PublisherIEEE Computer Society
Pages257-262
Number of pages6
ISBN (Print)9781538670996
DOIs
StatePublished - 7 Aug 2018
Event17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 - Hong Kong, Hong Kong
Duration: 9 Jul 201811 Jul 2018

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2018-July
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Conference

Conference17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
CountryHong Kong
CityHong Kong
Period9/07/1811/07/18

Keywords

  • Delay minimization synthesis flow
  • SET Array Blocks (SAB)
  • Single-Electron Transistor (SET)

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