Architecture exploration and delay minimization synthesis for set-based programmable gate arrays

Chia Cheng Wu; Kung Han Ho; Juinn-Dar Huang; Chun Yao Wang

doi:10.1109/ISVLSI.2018.00055

Architecture exploration and delay minimization synthesis for set-based programmable gate arrays

Chia Cheng Wu, Kung Han Ho, Juinn-Dar Huang, Chun Yao Wang

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Power consumption has become a primary obstacle for circuit designs at present. Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its low power consumption. Since, only a few electrons are involved in the switching process, the drivability of SETs is ultra-low such that the height of an SET array is limited to a small number. This paper presents a delay minimization synthesis flow that decomposes a circuit into a network of SET Array Blocks (SABs) with a fixed height and width. The experiments were conducted for different sizes of SABs over a set of benchmarks. The experimental results showed that we can have the smallest average Area Delay Product (ADP) when the height is 5 and the width is 10 of an SAB, which indicates that such size of SABs is proper to synthesize SET networks.

Original language	English
Title of host publication	Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
Publisher	IEEE Computer Society
Pages	257-262
Number of pages	6
ISBN (Print)	9781538670996
DOIs	https://doi.org/10.1109/ISVLSI.2018.00055
State	Published - 7 Aug 2018
Event	17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 - Hong Kong, Hong Kong Duration: 9 Jul 2018 → 11 Jul 2018

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2018-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
Country	Hong Kong
City	Hong Kong
Period	9/07/18 → 11/07/18

Keywords

Delay minimization synthesis flow
SET Array Blocks (SAB)
Single-Electron Transistor (SET)

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10.1109/ISVLSI.2018.00055

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Wu, C. C., Ho, K. H., Huang, J-D., & Wang, C. Y. (2018). Architecture exploration and delay minimization synthesis for set-based programmable gate arrays. In Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 (pp. 257-262). [8429376] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2018-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2018.00055

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abstract = "Power consumption has become a primary obstacle for circuit designs at present. Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its low power consumption. Since, only a few electrons are involved in the switching process, the drivability of SETs is ultra-low such that the height of an SET array is limited to a small number. This paper presents a delay minimization synthesis flow that decomposes a circuit into a network of SET Array Blocks (SABs) with a fixed height and width. The experiments were conducted for different sizes of SABs over a set of benchmarks. The experimental results showed that we can have the smallest average Area Delay Product (ADP) when the height is 5 and the width is 10 of an SAB, which indicates that such size of SABs is proper to synthesize SET networks.",

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author = "Wu, {Chia Cheng} and Ho, {Kung Han} and Juinn-Dar Huang and Wang, {Chun Yao}",

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Wu, CC, Ho, KH, Huang, J-D & Wang, CY 2018, Architecture exploration and delay minimization synthesis for set-based programmable gate arrays. in Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018., 8429376, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2018-July, IEEE Computer Society, pp. 257-262, 17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, Hong Kong, 9/07/18. https://doi.org/10.1109/ISVLSI.2018.00055

Architecture exploration and delay minimization synthesis for set-based programmable gate arrays. / Wu, Chia Cheng; Ho, Kung Han; Huang, Juinn-Dar; Wang, Chun Yao.

Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018. IEEE Computer Society, 2018. p. 257-262 8429376 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2018-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Power consumption has become a primary obstacle for circuit designs at present. Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its low power consumption. Since, only a few electrons are involved in the switching process, the drivability of SETs is ultra-low such that the height of an SET array is limited to a small number. This paper presents a delay minimization synthesis flow that decomposes a circuit into a network of SET Array Blocks (SABs) with a fixed height and width. The experiments were conducted for different sizes of SABs over a set of benchmarks. The experimental results showed that we can have the smallest average Area Delay Product (ADP) when the height is 5 and the width is 10 of an SAB, which indicates that such size of SABs is proper to synthesize SET networks.

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Wu CC, Ho KH, Huang J-D, Wang CY. Architecture exploration and delay minimization synthesis for set-based programmable gate arrays. In Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018. IEEE Computer Society. 2018. p. 257-262. 8429376. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). https://doi.org/10.1109/ISVLSI.2018.00055

Architecture exploration and delay minimization synthesis for set-based programmable gate arrays

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