Architecture design of QPP interleaver for parallel turbo decoding

Shuenn Gi Lee*, Chung-Hsuan Wang, Wern Ho Sheen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Quadratic permutation polynomial (QPP) interleaver has the advantage of contention-free for parallel memory access and has been adopted in the 3GPP LTE for turbo coding. Conventional implementations of the QPP interleaver based on the look-up table or on-line calculation usually result in large circuit area or higher clock rate for parallel turbo decoding. In this paper, an architecture design of QPP interleaver for parallel turbo decoding is presented which can provide parallel memory access without extra storage of interleaving patterns or the increment of clock rate compared with the conventional approaches. The proposed design is also reconfigurable for variable interleaver lengths.

Original languageEnglish
Title of host publication2010 IEEE 71st Vehicular Technology
DOIs
StatePublished - 30 Jul 2010
Event2010 IEEE 71st Vehicular Technology Conference, VTC 2010-Spring - Taipei, Taiwan
Duration: 16 May 201019 May 2010

Publication series

NameIEEE Vehicular Technology Conference
ISSN (Print)1550-2252

Conference

Conference2010 IEEE 71st Vehicular Technology Conference, VTC 2010-Spring
CountryTaiwan
CityTaipei
Period16/05/1019/05/10

Keywords

  • Parallel decoding
  • QPP interleaver
  • Variable interleaver lengths

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    Lee, S. G., Wang, C-H., & Sheen, W. H. (2010). Architecture design of QPP interleaver for parallel turbo decoding. In 2010 IEEE 71st Vehicular Technology [5493793] (IEEE Vehicular Technology Conference). https://doi.org/10.1109/VETECS.2010.5493793