Architecture design of MPEG-4 texture decoder supporting object-based video coding

Hui Cheng Hsu*, N. Y C Chang, Tian-Sheuan Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Handling of the complexity which arises due the irregularity data nature for MPEG-4 object based video coding is an important issue in MPEG-4 texture decoder design. Another crucial issue is designing an efficient architecture to satisfy the resource sensitive nature of portable embedded video codec systems. This paper presents an architecture for texture decoding to address these two major issues. By adopting zero-skipping and zero index tables together, the throughput and power consumption are improved significantly. To avoid incurring extra hardware overhead, multiplication sharing and buffer sharing are also incorporated. The synthesized design can perform texture decoding of CIF@30FPS under 2.18 MHz. using UMC 0.18μm 1P6M technology, the reported power consumption is 0.92 mW.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages275-278
Number of pages4
DOIs
StatePublished - 1 Dec 2005
Event2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
Duration: 27 Apr 200529 Apr 2005

Publication series

Name2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Volume2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
CountryTaiwan
CityHsinchu
Period27/04/0529/04/05

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