Architecture design of full HD JPEG XR encoder for digital photography applications

Chia Ho Pan*, Ching Yen Chien, Wei Min Chao, Sheng-Chieh Huang, Liang Gee Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

19 Scopus citations


To satisfy the high quality image compression requirement, the new JPEG XR compression standard is introduced. The analysis and architecture design with VLSI architecture of JPEG XR encoder are proposed in this paper which can encode 4:4:4 1920 x 1080 high definition photo in smooth. According to the simulation results, the throughput of the proposed design can encode 44.2 M samples/sec. This design can be used for digital photography applications to achieve low computation, low storage, and high dynamical range features.

Original languageAmerican English
Pages (from-to)963-971
Number of pages9
JournalIEEE Transactions on Consumer Electronics
Issue number3
StatePublished - 28 Oct 2008


  • High definition photo
  • Joint Photographic Experts Group (JPEG)
  • VLSI architecture

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