Architectural synthesis frameworks on distributed register-file microarchitecture family

Chia I. Chen*, Juinn-Dar Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work, we first develop a communication synthesis framework targeting the original DRFM. The algorithm aims to optimize both interconnect resources (IIC) and system performance (latency). Then we propose a new distributed register-file based platform-DRFM-IID, where the delay model is one step toward reality. Furthermore, a dedicated synthesis framework for DRFM-IID, which focuses on minimizing the system latency and power consumption simultaneously, is also proposed. We thoroughly investigate all existing woks about distributed register-file microarchitecture family with variant inter-island delay models, and the experimental results indicate that our work does provide better synthesis outcome than the prior art.

Original languageEnglish
Title of host publicationProceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Pages369-370
Number of pages2
DOIs
StatePublished - 14 Sep 2011
Event2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 - Chennai, India
Duration: 4 Jul 20116 Jul 2011

Publication series

NameProceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Conference

Conference2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
CountryIndia
CityChennai
Period4/07/116/07/11

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