In this work, applicability of established semiclassical (SC) simulation techniques to ultra-short gate MOS devices is discussed and comparisons between experimental data of MOS transistors with gate down to 40 nm and simulation results are reported. Finally, examples of applications to the comparison of different device structures are reported.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1994|
|Event||Proceedings of the 1994 IEEE International Electron Devices Meeting - San Francisco, CA, USA|
Duration: 11 Dec 1994 → 14 Dec 1994