Application-dependent scaling tradeoffs and optimization in the SoC Era

Carlos H. Díaz*, Mi Chang Chang, T. C. Ong, Jack Sun

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

Several physical phenomena in highly scaled CMOS technology have now become first order elements affecting electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others, have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.

Original languageEnglish
Pages (from-to)475-478
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 2002
EventIEEE 2002 Custom Integrated Circuits Conference - Orlando, FL, United States
Duration: 12 May 200215 May 2002

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