Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology

Hsin Chieh Chen; Wei Chung Chen; Ying Wei Chou; Meng Wei Chien; Chin Long Wey; Ke-Horng Chen; Ying Hsi Lin; Tsung Yen Tsai; Chao Cheng Lee

doi:10.1109/CICC.2014.6946134

Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology

Hsin Chieh Chen, Wei Chung Chen, Ying Wei Chou, Meng Wei Chien, Chin Long Wey, Ke-Horng Chen, Ying Hsi Lin, Tsung Yen Tsai, Chao Cheng Lee

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Conventional constant-on-time (COT) control for DC-DC buck converter is apt to be affected by the noise caused by parasitic effect including not properly specified and temperature dependent equivalent series resistance (ESR) and equivalent series inductance (ESL). As a result, the safety operation area (SOA) of the COT is limited by the selection of external components. In this paper, the calibrated anti-ESL (CAESL) technique and the calibrated gain and BW (CGB) technique for alleviating ESL and ESR variation, respectively, are proposed to ensure a robust COT control. Furthermore, degraded output regulation caused by enlarged ESL effect due to input battery voltage variation is also solved by the CAESL technique. The proposed COT converter fabricated in 28nm CMOS technology uses an output capacitor with an ESR smaller than 1m, output ripple of 20mV, and high efficiency higher than 95%. The CAESL circuit can tolerate ESL voltage variation from 0 to 50mV even when operation temperature varies from -40 to 120°C.

Original language	English
Title of host publication	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479932863
DOIs	https://doi.org/10.1109/CICC.2014.6946134
State	Published - 4 Nov 2014
Event	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States Duration: 15 Sep 2014 → 17 Sep 2014

Publication series

Name	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Conference

Conference	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
Country	United States
City	San Jose
Period	15/09/14 → 17/09/14

Keywords

calibrated anti-ESL (CAESL)
calibrated gain and BW (CGB)
equivalent series inductor (ESL)
equivalent series resistance (ESR)

Access to Document

10.1109/CICC.2014.6946134

Link to publication in Scopus

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Chen, H. C., Chen, W. C., Chou, Y. W., Chien, M. W., Wey, C. L., Chen, K-H., Lin, Y. H., Tsai, T. Y., & Lee, C. C. (2014). Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 [6946134] (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2014.6946134

Chen, Hsin Chieh ; Chen, Wei Chung ; Chou, Ying Wei ; Chien, Meng Wei ; Wey, Chin Long ; Chen, Ke-Horng ; Lin, Ying Hsi ; Tsai, Tsung Yen ; Lee, Chao Cheng. / Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology. Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

@inproceedings{75a8204c9e9042cfb41b2bd160249799,

title = "Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology",

abstract = "Conventional constant-on-time (COT) control for DC-DC buck converter is apt to be affected by the noise caused by parasitic effect including not properly specified and temperature dependent equivalent series resistance (ESR) and equivalent series inductance (ESL). As a result, the safety operation area (SOA) of the COT is limited by the selection of external components. In this paper, the calibrated anti-ESL (CAESL) technique and the calibrated gain and BW (CGB) technique for alleviating ESL and ESR variation, respectively, are proposed to ensure a robust COT control. Furthermore, degraded output regulation caused by enlarged ESL effect due to input battery voltage variation is also solved by the CAESL technique. The proposed COT converter fabricated in 28nm CMOS technology uses an output capacitor with an ESR smaller than 1m, output ripple of 20mV, and high efficiency higher than 95%. The CAESL circuit can tolerate ESL voltage variation from 0 to 50mV even when operation temperature varies from -40 to 120°C.",

keywords = "calibrated anti-ESL (CAESL), calibrated gain and BW (CGB), equivalent series inductor (ESL), equivalent series resistance (ESR)",

author = "Chen, {Hsin Chieh} and Chen, {Wei Chung} and Chou, {Ying Wei} and Chien, {Meng Wei} and Wey, {Chin Long} and Ke-Horng Chen and Lin, {Ying Hsi} and Tsai, {Tsung Yen} and Lee, {Chao Cheng}",

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doi = "10.1109/CICC.2014.6946134",

language = "English",

series = "Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014",

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Chen, HC, Chen, WC, Chou, YW, Chien, MW, Wey, CL, Chen, K-H, Lin, YH, Tsai, TY & Lee, CC 2014, Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology. in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014., 6946134, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, Institute of Electrical and Electronics Engineers Inc., 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014, San Jose, United States, 15/09/14. https://doi.org/10.1109/CICC.2014.6946134

Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology. / Chen, Hsin Chieh; Chen, Wei Chung; Chou, Ying Wei; Chien, Meng Wei; Wey, Chin Long; Chen, Ke-Horng; Lin, Ying Hsi; Tsai, Tsung Yen; Lee, Chao Cheng.

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6946134 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology

AU - Chen, Hsin Chieh

AU - Chen, Wei Chung

AU - Chou, Ying Wei

AU - Chien, Meng Wei

AU - Wey, Chin Long

AU - Chen, Ke-Horng

AU - Lin, Ying Hsi

AU - Tsai, Tsung Yen

AU - Lee, Chao Cheng

PY - 2014/11/4

Y1 - 2014/11/4

N2 - Conventional constant-on-time (COT) control for DC-DC buck converter is apt to be affected by the noise caused by parasitic effect including not properly specified and temperature dependent equivalent series resistance (ESR) and equivalent series inductance (ESL). As a result, the safety operation area (SOA) of the COT is limited by the selection of external components. In this paper, the calibrated anti-ESL (CAESL) technique and the calibrated gain and BW (CGB) technique for alleviating ESL and ESR variation, respectively, are proposed to ensure a robust COT control. Furthermore, degraded output regulation caused by enlarged ESL effect due to input battery voltage variation is also solved by the CAESL technique. The proposed COT converter fabricated in 28nm CMOS technology uses an output capacitor with an ESR smaller than 1m, output ripple of 20mV, and high efficiency higher than 95%. The CAESL circuit can tolerate ESL voltage variation from 0 to 50mV even when operation temperature varies from -40 to 120°C.

AB - Conventional constant-on-time (COT) control for DC-DC buck converter is apt to be affected by the noise caused by parasitic effect including not properly specified and temperature dependent equivalent series resistance (ESR) and equivalent series inductance (ESL). As a result, the safety operation area (SOA) of the COT is limited by the selection of external components. In this paper, the calibrated anti-ESL (CAESL) technique and the calibrated gain and BW (CGB) technique for alleviating ESL and ESR variation, respectively, are proposed to ensure a robust COT control. Furthermore, degraded output regulation caused by enlarged ESL effect due to input battery voltage variation is also solved by the CAESL technique. The proposed COT converter fabricated in 28nm CMOS technology uses an output capacitor with an ESR smaller than 1m, output ripple of 20mV, and high efficiency higher than 95%. The CAESL circuit can tolerate ESL voltage variation from 0 to 50mV even when operation temperature varies from -40 to 120°C.

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KW - calibrated gain and BW (CGB)

KW - equivalent series inductor (ESL)

KW - equivalent series resistance (ESR)

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DO - 10.1109/CICC.2014.6946134

M3 - Conference contribution

AN - SCOPUS:84928154794

T3 - Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

BT - Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 15 September 2014 through 17 September 2014

ER -

Chen HC, Chen WC, Chou YW, Chien MW, Wey CL, Chen K-H et al. Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6946134. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). https://doi.org/10.1109/CICC.2014.6946134