Anomalous substrate current in polycrystalline silicon thin-film transistors

Hsiao-Wen Zan*, Shih Ching Chen, Sheng Hsuan Wang, Chun Yen Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, the substrate current of polycrystalline silicon thin-film transistors was measured and investigated for the first time. With a typical T-gate patterned structure, an abnormally high substrate current was found while devices were operated under high gate voltage. This is generated from the parasitic tunnelling current between the n+ inversion region and the p+ body region. Under lower gate voltage, a substrate current generated from impact ionization effects is also observed and characterized. After extracting fitting parameters from the device characteristics, a simple physically-based model was established and compared with the measured results. A plausible grain boundary scattering effect was included in the proposed model. Good agreement was found through a wide range of gate bias and various drain bias conditions, verifying the validity of this unified model.

Original languageEnglish
Title of host publicationESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference
EditorsJose Franca, Paulo Freitas
PublisherIEEE Computer Society
Pages469-472
Number of pages4
ISBN (Electronic)0780379993
ISBN (Print)9780780379992
DOIs
StatePublished - 1 Jan 2003
Event33rd European Solid-State Device Research Conference, ESSDERC 2003 - Estoril, Portugal
Duration: 16 Sep 200318 Sep 2003

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference33rd European Solid-State Device Research Conference, ESSDERC 2003
CountryPortugal
CityEstoril
Period16/09/0318/09/03

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