In this paper, the substrate current of polycrystalline silicon thin-film transistors was measured and investigated for the first time. With a typical T-gate patterned structure, an abnormally high substrate current was found while devices were operated under high gate voltage. This is generated from the parasitic tunnelling current between the n+ inversion region and the p+ body region. Under lower gate voltage, a substrate current generated from impact ionization effects is also observed and characterized. After extracting fitting parameters from the device characteristics, a simple physically-based model was established and compared with the measured results. A plausible grain boundary scattering effect was included in the proposed model. Good agreement was found through a wide range of gate bias and various drain bias conditions, verifying the validity of this unified model.