Analyzing cache performance on multi-stream execution processor

Chih Zong Lin*, Chien-Chao Tseng, Chung-Ping Chung

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, effect of multi-stream (or multithreaded) execution on the performance of cache system is presented. Parameters considered include cache size, line size, set associativity, and unification of instruction/data. The results presented in this paper can be used when designing a multithreaded processor system.

Original languageEnglish
Title of host publicationProceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering
PublisherPubl by IEEE
Pages1-4
Number of pages4
ISBN (Print)0780312333
DOIs
StatePublished - 1 Dec 1993
EventProceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5) - Beijing, China
Duration: 19 Oct 199321 Oct 1993

Publication series

NameProceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering

Conference

ConferenceProceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5)
CityBeijing, China
Period19/10/9321/10/93

Cite this