An analytical model for describing the drain current characteristics of gate-all-around (GAA) tunneling field-effect transistor (TFET) is developed. Starting from potential distribution derived from Poisson's equation in different regions along the channel, drain current model is developed based on Kane's approach. The new model shows a better accuracy than the previously reported models. It is valid for larger ranges of bias conditions and channel length also. In particular, we have taken the effect of drain bias on the source junction tunneling into account. This effect is quite significant for the subthreshold conduction of short-channel devices. The validity of this model has been confirmed with TCAD simulation.