A scheme for scaling-down of the silicon analog bipolar transistors has been investigated in detail in terms of power consumption, noise figure and associated power gain. There is an appropriate scaling approach for the analog bipolars.
|Number of pages||4|
|State||Published - 1994|
|Event||Proceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA|
Duration: 10 Oct 1994 → 11 Oct 1994
|Conference||Proceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting|
|City||Minneapolis, MN, USA|
|Period||10/10/94 → 11/10/94|