Analysis of silicon bipolar transistor scaling-down scheme for low noise and low power analog application

Nobuyuki Itoh*, Yoshihiro Yoshida, Shuji Watanabe, Yasuhiro Katsumata, Hiroshi Iwai

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

A scheme for scaling-down of the silicon analog bipolar transistors has been investigated in detail in terms of power consumption, noise figure and associated power gain. There is an appropriate scaling approach for the analog bipolars.

Original languageEnglish
Pages60-63
Number of pages4
StatePublished - 1994
EventProceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA
Duration: 10 Oct 199411 Oct 1994

Conference

ConferenceProceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting
CityMinneapolis, MN, USA
Period10/10/9411/10/94

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