Analysis of poly-Si TFT degradation under gate pulse stress using the slicing model

Ya-Hsiang Tai*, Shih Cheh Huang, Chien Kwen Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

29 Scopus citations

Abstract

The device degradation of polycrystalline-silicon thin-film transistors stressed with different gate pulse waveforms is investigated. It is first observed that the degradation is dependent on the rising time of the gate pulses for the gate voltage swing below the threshold voltage. The degradation ratio of the mobility is analyzed with respect to two factors, namely, the magnitude of the lateral transient electric field and the change in the numbers of the carrier near the edges of the channel. A new index considering these two factors is proposed to depict the device degradation. It shows good linearity between the degradation in mobility and the proposed index.

Original languageEnglish
Pages (from-to)981-983
Number of pages3
JournalIEEE Electron Device Letters
Volume27
Issue number12
DOIs
StatePublished - 1 Dec 2006

Keywords

  • AC stress
  • Dynamic stress
  • Poly-Si thin-film transistors (TFTs)
  • Reliability

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