We have performed a two-dimensional analysis to study the interface trap effects on the drain current degradation in submicron MOSFET's. A hot electron stress induced interface trap generation model has been developed. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 urn LDD MOSFET was stressed at Vds=7V and Vgs=3V for 104 seconds. The drain current degradation was characterized in both normal mode and reverse mode to compare the simulation. Our study shows that a significant drain current reduction appears in the linear region while the current reduction is only a few percentage points in the saturation region in normal mode. In reverse mode, the drain current degradation is significant in the entire region of operation.
|State||Published - 1 Jan 1994|
|Event||1994 International Electron Devices and Materials Symposium, EDMS 1994 - Hsinchu, Taiwan|
Duration: 12 Jul 1994 → 15 Jul 1994
|Conference||1994 International Electron Devices and Materials Symposium, EDMS 1994|
|Period||12/07/94 → 15/07/94|