Analysis of interface state induced performance variation in LDD MOSFET's

Ta-Hui Wang, C. Huang, P. C. Chou, Steve S. Chung, T. E. Chang

Research output: Contribution to conferencePaper

Abstract

We have performed a two-dimensional analysis to study the interface trap effects on the drain current degradation in submicron MOSFET's. A hot electron stress induced interface trap generation model has been developed. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 urn LDD MOSFET was stressed at Vds=7V and Vgs=3V for 104 seconds. The drain current degradation was characterized in both normal mode and reverse mode to compare the simulation. Our study shows that a significant drain current reduction appears in the linear region while the current reduction is only a few percentage points in the saturation region in normal mode. In reverse mode, the drain current degradation is significant in the entire region of operation.

Original languageEnglish
DOIs
StatePublished - 1 Jan 1994
Event1994 International Electron Devices and Materials Symposium, EDMS 1994 - Hsinchu, Taiwan
Duration: 12 Jul 199415 Jul 1994

Conference

Conference1994 International Electron Devices and Materials Symposium, EDMS 1994
CountryTaiwan
CityHsinchu
Period12/07/9415/07/94

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    Wang, T-H., Huang, C., Chou, P. C., Chung, S. S., & Chang, T. E. (1994). Analysis of interface state induced performance variation in LDD MOSFET's. Paper presented at 1994 International Electron Devices and Materials Symposium, EDMS 1994, Hsinchu, Taiwan. https://doi.org/10.1109/EDMS.1994.863897