Analysis of Hot-Carrier-Induced Degradation Mode on pMOSFET’s

Fumitomo Matsuoka, Hiroshi Iwai, Hiroyuki Hayashida, Kaoru Hama, Yoshiaki Toyoshima, Kenji Maeguchi

Research output: Contribution to journalArticlepeer-review

58 Scopus citations

Abstract

Hot-carrier-induced degradation has been studied both for surface-channel (p+ polysilicon gate) and for huried-channel (n + polysilicon gate) pMOSFET’s. In the shallow gate bias region, a new hot-carrier degradation mode by drain avalanche hot hole injection was found for the surface-channel pMOSFET’s. Here, trapped holes and interface state generation, which were not observed in the buried-channel pMOSFET’s, were detected. It was confirmed that, in this gate bias region, the degradation for the surface-channel structure is smaller than that for the buried-channel structure. It was found that there are at least three reasons for the smaller degradation in the surface-channel structure. The first reason is smaller gate injection current for the surface-channel structure due to the metal work function difference between p+ and n+ poly gates. The second reason is the smaller potential change in the channel for the same amount of trapped charge. The third reason is the compensation of some amount of trapped electrons by injected holes. The deep-gate bias region was also investigated. In this region, an interface-state generation mode without the threshold-voltage shift was found for both surface-and buried-channel pMOSFET’s. It was confirmed that this interface state generation is caused by channel hot hole injection.

Original languageEnglish
Pages (from-to)1487-1495
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume37
Issue number6
DOIs
StatePublished - Jun 1990

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